Standard specified hash algorithms can be used to generate digests (hash values) of messages. The digests are used to detect whether messages have been changed since the digests have been generated. In last few years, there have been some research and trend toward hardware implementation of security algorithms for speeding up the security process.
Since the Secure Hash Algorithm (SHA) functions are one-way and chances of collision are very rare, the hash value calculation changes substantially for minor changes to the input file. The Secure Hash Algorithm 2 (SHA-2) was further developed to generate a unique 256-bit (SHA-256), 224-bit (SHA-224), or 512-bit (SHA-512) message digest for any message.
Previous implementation of the SHA-2 in software has been quite slow as each round of the SHA-2 computations takes multiple instructions and clock cycles. Although single instruction, multiple data (SIMD) computation was created for some reduced instruction set computing (RISC) processors to speed up the SHA-2 processing, it still takes hundreds of clock cycles to generate an SHA-2 value. Most hardware implementations of the SHA-2 are slow as each SHA-2 hash calculation takes 64 clocks to process data, leading to a new message digest being generated every 64 clock cycles and making the design extremely slow.
There is an increasing demand for data processing invoking the SHA-2 algorithm than before. There is a need to create a novel system design to speed up implementations of SHA-2 algorithm. Furthermore, hardware implementations of SHA-2 may be tailored to specific applications.